The performance of computers is mainly determined by their speed of operation which is governed by the
Processor and Memory. In order to improve the speed of a computer, both the Processor and main Memory design
must be improved. Hence, this research work is aimed at increasing the main memory speed of a computer by
redesigning the components that make up the computer main memory. The design of basic memory devices, using the
different Memory Elements developed from practical experimentation, analytical and numerical frameworks, was
done. Analysis of each design was established using Propagation Route Framework in order to determine which of
them gave higher computer speed. It was observed that the number of transitions required to complete a propagation
route in the proposed SET/RESET memory element tagged SRALT shows an operational maximum number of fourteen
(14) transistors as against sixteen (16) transistors of the conventional SET/RESET memory element tagged SRCONV.
Likewise, the SRALT maximum data route delay passes through (3) gates as against SRCONV that has its maximum data
route delay passing through (4) gates. Thus the delay was drastically reduced, thereby increasing the speed of the
computer processing when compared with the conventional (SRCONV), commercially available RAMs.